Establishing a Power and Time Optimized Serial Communication Link for High-end Transceivers

Authors:A.SUSMITHA, CH.BALAKRISHNA, A.ENOCH

0920-0923

A New Approach for Power and Latency Reduction by using C-Element in Digital Integrated Circuits

Authors:KUNAM DIVYA, AZMEE RAVI

0924-0927

Design of an Error Detection and Data Recovery Architecture for Motion Estimation Computing Array

Authors:D.LEELA BHUVANESWRI, V.AMARESWAR

0928-932

An Implementation of Assertion Based Verification (ABV) Algorithm for DDR Memory Cores

Authors:KORUKONDA SAILESH, S.Ranjitha

0933-0936

Realization of 32-Bit Unsigned Multiplier using CLAA CSLA and Spanning Tree Adder for High Speed Operations

Authors:D.S.REVATHI, CHAYA SHANKAR

0937-0942

Reduced-Complexity Reed–Solomon Encoder Based on Galois Field

Authors:PULLAKANTI ASHALATHA, V.DAMODAR

0943-0949

Implementation of Low power and High Speed Array Multiplier Using Bi-CMOS Technology for Driving Large Load

Authors:VENNALA VASAVI, D.KHALANDAR BASHA

0950-0954